The present invention relates to CMOS image sensors. More specifically, the present invention relates to CMOS active pixel sensors without field oxide isolation around the photodiode diffusion region of each pixel.
Solid state image sensors used in, for example, video cameras are presently realized in a number of forms including charge coupled devices (CCDs) and CMOS image sensors. These image sensors are based on a two dimensional array of pixels. Each pixel includes a sensing element that is capable of converting a portion of an optical image into an electronic signal. These electronic signals are then used to regenerate the optical image on, for example, a cathode-ray tube (CRT) display.
CMOS image sensors first appeared in 1967. However, CCDs have prevailed since their invention in 1970. Both solid-state imaging sensors depend on the photovoltaic response that results when silicon is exposed to light. Photons in the visible and near-IR regions of the spectrum have sufficient energy to break covalent bonds in silicon. The number of electrons released is proportional to the light intensity. Even though both technologies use the same physical properties, all-analog CCDs dominate vision applications because of their superior dynamic range, low fixed-pattern noise (FPN), and high sensitivity to light.
More recently, however, CMOS image sensors have gained in popularity. Pure CMOS image sensors have benefited from advances in CMOS technology for microprocessors and ASICs and provide several advantages over CCD imagers. Shrinking lithography and advanced signal-processing algorithms set the stage for sensor array, array control, and image processing on one chip produced using these well-established CMOS techniques. Shrinking lithography should also decrease image-array cost due to smaller pixels. However, pixels cannot shrink too much, or they have an insufficient light-sensitive area. Nonetheless, shrinking lithography provides reduced metal-line widths that connect transistors and buses in the array. This reduction of metal-line widths exposes more silicon to light, thereby increasing light sensitivity. CMOS image sensors also provide greater power savings because they require fewer power-supply voltages than do CCD imagers. In addition, due to modifications to CMOS pixels, newly developed CMOS image sensors provide high-resolution, low-noise images that are comparable with CCD imager quality.
CMOS pixel arrays are at the heart of the newly developed CMOS image sensors. CMOS pixel-array construction uses active or passive pixels.
Each pixel of a passive pixel array includes a photodiode for converting photon energy to free electrons, and an access transistor for selectively connecting the photodiode to a column bus. However, high read noise for passive pixels limit the passive pixel array""s size. Further, the turn-on thresholds for the access transistors of the various pixels varies throughout the passive pixel array, thereby giving non-uniform response to identical light levels.
CMOS active-pixel sensors (APSs) overcome passive-pixel deficiencies by including active circuits (transistors) in each pixel. In one example, these active circuits include a source-follower transistor, a reset transistor and a row-selection transistor. The source-follower transistor buffers the charge transferred to an output (column) bus from the light sensing element (i.e., photodiode or photogate), and provides current to quickly charge and discharge the bus capacitance. The faster charging and discharging allow the bus length to increase. This increased bus length, in turn, allows an increase in the array size. The reset transistor controls integration time and, therefore, provides for electronic shutter control. The row-select transistor gives half the coordinate readout capability to the array. Although these transistors would appear to increase the device""s power consumption, little difference exists between an active and a passive pixel""s power consumption.
FIG. 1 shows a conventional CMOS APS that includes a pixel array 10, a row decoder 20 and a plurality of column data (bus) lines 30. Pixel array 10 includes closely spaced APS cells (pixels) 100 that are arranged in rows and columns. Pixel array 10 is depicted as a ten-by-ten array for illustrative purposes only. Pixel arrays typically consist of a much larger number of pixels (e.g., 1280-by-1024 arrays).
Each APS cell 100 of pixel array 10 includes a light sensing element and the active circuits described above. The light sensing element is capable of converting a detected quantity of light into a corresponding electrical signal at an output terminal 50. The active circuits of pixels in each row are connected to a common reset control line 23 and a common row select control line 27. The active circuits of the pixels in each column are connected through respective output terminals 50 to common column data lines 30.
In operation, a timing controller (not shown) provides timing signals to row decoder 20 that sequentially activates each row of APS cells 100 using control signals transmitted via reset control lines 23 and row select control lines 27 to detect light intensity and to generate corresponding output voltage signals during each frame interval. A frame, as used herein, refers to a single complete cycle of activating and sensing the output from each APS cell 100 in the array over a predetermined frame time period. The timing of the imaging system is controlled to achieve a desired frame rate, such as 30 frames per second. The detailed circuitry of the row decoder 20 is well known to one of ordinary skill in the art of CMOS APS production.
When detecting a particular frame, each row of pixels may be activated to detect light intensity over a substantial portion of the frame interval. In the time remaining after the row of APS cells 100 has detected the light intensity for the frame, each of the respective pixels simultaneously generates output voltage signals corresponding to the amount of light detected by that APS cell 100. If an image is focused on the array 10 by, for example, a conventional camera lens, then each APS cell 100 generates an output voltage signal corresponding to the light intensity for a portion of the image focused on that APS cell 100. The output voltage signals generated by the activated row are simultaneously provided to the column output line 30 via output terminals 50.
FIGS. 2(A) and 2(B) are plan and cross-sectional side views, respectively, showing a portion of a conventional CMOS APS cell 100. Referring to FIG. 2(B), which is a cross-sectional side view taken along line 2Bxe2x80x942B of FIG. 2(A), conventional CMOS APS cell 100 includes a photodiode region 102 having a peripheral edge that is surrounded by field oxide 104. An interface 106 is defined along the abutting peripheral edges of photodiode region 102 and field oxide 104. In addition, a reset gate 107 is located over a channel 103 provided between a source region 108 and a drain region 109. Reset gate 107 controls charging and discharging of photodiode region 102 via source region 108, which extends from photodiode region 102, in the manner described above.
Based on conventional practices, the fabrication of CMOS APS cell 100 begins by growing field oxide 104 using the well-known LOCOS (LOCal Oxidation of Silicon) process to isolate photodiode region 102 from currents generated in surrounding pixels. Next, polysilicon is deposited and patterned to form reset gate 107. Reset gate 107 and field oxide 104 are then used to form lightly-doped drain (LDD) regions in source region 108 and drain region 109. Next, sidewall spacers, such as sidewall spacer 110 shown in FIG. 2(B), are formed using a plasma oxide etch process. Finally, photodiode region 102, source region 108 and drain region 109 are heavily (n+) doped, and metal contacts (not shown) are provided to, for example, connect a reset control line 23 (see FIG. 1) to reset gate 107.
A problem associated with conventional CMOS APSs is that growth of field oxide using LOCOS processes induces mechanical stress at the field oxide""s bird""s beak region. Therefore, conventional CMOS APS pixel arrays often experience white spots in the image generated by a CMOS APS.
What is needed is a method for fabricating pixel sensor structures that minimizes the occurrence of white spots on images produced by CMOS image sensors without reduction of the fill factor of CMOS APS pixel arrays.
The present inventors have determined that a significant cause of white spot problems in CMOS image sensors is excessive current leakage from the light-sensitive (e.g., photodiode) regions. In particular, this excessive current leakage appears to occur at the interface between the photodiode diffusion region and the surrounding field oxide. These interface regions are subjected to excessive mechanical stress and damage during the LOCOS process used to form the field oxide, and to excessive electrical stress during device operation. These mechanical and electrical stresses are believed to be the primary cause of excessive leakage current that results in white spots.
Accordingly, the present invention provides a fieldless CMOS image sensor and methods for producing the fieldless CMOS image sensor that utilize field isolation materials other than LOCOS-based field oxide around the peripheral edge of the photodiode diffusion region. By eliminating LOCOS-based field oxide from the peripheral edge of the light sensitive regions, the stress/damage produced in prior art image sensors is avoided. Therefore, leakage current from the light sensitive regions is reduced, and the occurrence of white spots is minimized.
In accordance with an embodiment of the present invention, a fieldless CMOS image sensor includes at least one pixel that has an image-sensing region having a peripheral edge and an isolation structure formed around the image-sensing region that includes spacer oxide structures located over an anti-punchthrough (APT) implant (which includes a conventional anti-punchthrough implant, a threshold voltage adjust implant and a PLDD implant). The spacer oxide structures are formed from a spacer oxide layer using a special blocking mask. The spacer oxide structures are utilized to shield the APT implant regions during heavy doping of the image-sensing region. Consequently, the stress/damage produced in the conventional CMOS APS cell is avoided using an economical process that requires only one additional mask.
The present invention will be more fully understood in view of the following description and drawings.